The present invention relates to a semiconductor device, and more particularly to a phase locked loop (PLL), which can ensure a fast locking time, and a method for operating the same.
In semiconductor devices such as double data rate (DDR) synchronous dynamic random access memory (SDRAM), an external clock is used as a reference to match operation timings. However, a clock skew may occur in the external clock due to the delay in clock/data path of internal circuits. In order to compensate the clock skew, a clock synchronization circuit is provided within the semiconductor device. Examples of the clock synchronization circuit include a phase locked loop (PLL) and a delay locked loop (DLL). The semiconductor device transmits/receives signals to/from external devices by using an internal clock outputted from the clock synchronization circuit.
The PLL having a frequency multiplication function is mainly used when the frequency of the external clock is different from the frequency of the internal clock, and the DLL is mainly used when the frequency of the external clock is equal to the frequency of the internal clock. The configuration of the PLL is basically similar to that of the DLL. The PLL uses a voltage controlled oscillator (VCO) to generate the internal clock, while the DLL uses a voltage controlled delay line (VCDL).
Compared with the DLL, the PLL occupies a large chip area and is difficult to design, but it can generate various clocks through frequency synthesis and can easily achieve a clock data recovery (CDR). Therefore, the PLL is used in a variety of applications, e.g., communications, wireless systems, digital circuits, etc. As the operating speed of the chip is increasing, the PLL is essential to designing high-speed semiconductor devices with high operating frequency. It is expected that the application fields of the PLL will be widely expanded with rapid development of semiconductor device design technology.
FIG. 1 is a block diagram of a conventional PLL.
Referring to FIG. 1, the PLL includes a phase detector 110, a control voltage generator 130, a voltage control oscillator (VCO) 150. The phase detector 110 detects a phase difference between a reference clock CLK_REF and a feedback clock CLK_FED to generate detection signals DET_UP and DET_DN corresponding to the detected phase difference. The control voltage generator 130 receives the detection signals DET_UP and DET_DN to generate a control voltage V_CTR having a voltage level corresponding to the detection signals DET_UP and DET_DN. The VCO 150 generates an internal clock CLK_INN having a frequency corresponding to the control voltage V_CTR. A frequency divider 170 may be further included which divides the frequency of the internal clock CLK_INN to generate the feedback clock CLK_FED.
The phase detector 110 generates the up detection signal DET_UP and the down detection signal DET_DN according to the phase difference between the reference clock CLK_REF and the feedback clock CLK_FED. The up detection signal DET_UP is a pulse signal enabled when the phase of the feedback signal CLK_FED lags behind the phase of the reference clock CLK_REF, and it has a pulse width corresponding to the phase difference between the feedback signal CLK_FED and the reference clock CLK_REF. The down detection signal DET_DN is a pulse signal enabled when the phase of the feedback signal CLK_FED leads the phase of the reference clock CLK_REF, and it has a pulse width corresponding to the phase difference between the feedback signal CLK_FED and the reference clock CLK_REF.
The control voltage generator 130 includes a charge pump 132 and a loop filter 134. The charge pump 132 controls a current to be supplied to the loop filter 134 according to the pulse width of the up detection signal DET_UP and the down detection signal DET_DN. The loop filter 134 generates the control voltage V_CTR by charging or discharging the supplied current.
The VCO 150 generates an internal clock CLK_INN having a frequency corresponding to a voltage level of the control voltage V_CTR. For example, as the voltage level of the control voltage V_CTR becomes higher, the frequency of the internal clock CLK_INN becomes higher. As the voltage level of the control voltage V_CTR becomes lower, the frequency of the internal clock CLK_INN becomes lower.
The frequency divider 170 generates the feedback clock CLK_FED having a frequency lower than the internal clock CLK_INN in order to use a crystal oscillator as a reference frequency source. The crystal oscillator can maintain the reference clock CLK_REF at the correct frequency even in a change of surroundings. The phase detector 110 compares the feedback clock CLK_FED of a low frequency with the reference clock CLK_REF of a low frequency.
The PLL generates the internal clock CLK_INN having a desired frequency by repeating the locking operation until the frequency of the reference clock CLK_REF is equal to that of the feedback clock CLK_FED. The term “locking” means that the internal clock CLK_INN has a desired target frequency.
FIG. 2 is a block diagram of the phase detector 110 illustrated in FIG. 1.
Referring to FIG. 2, the phase detector 110 includes a first D flip-flop 112, a second D flip-flop 114, and a logic gate AND1. The first D flip-flop 112 is configured to generate the up detection signal DET_UP in response to the reference clock CLK_REF. The second D flip-flop 114 is configured to generate the down detection signal DET_DN in response to the feedback clock CLK_FED. The logic gate AND1 is configured to receive the up detection signal DET_UP and the down detection signal DET_DN to generate a reset signal CTR_RST resetting the first and second D flip-flops 112 and 114.
The phase detector 110 generates the up detection signal DET_UP of a logic high level when the reference clock CLK_REF is at a high level, and generates the down detection signal DET_DN of a logic high level when the feedback clock CLK_FED is at a logic high level. The phase detector 110 activates the reset signal CTR_RST to reset the first and second D flip-flops 112 and 14 when the reference clock CLK_REF and the feedback clock CLK_FED are all at a logic high level.
Consequently, when the phase of the reference clock CLK_REF leads that of the feedback clock CLK_FED, the phase detector 110 generates the up detection signal DET_UP having a pulse width corresponding to the phase difference between the reference clock CLK_REF and the feedback clock CLK_FED. When the phase of the feedback clock CLK_FED leads that of the reference clock CLK_REF, the phase detector 110 generates the down detection signal DET_DN having a pulse width corresponding to the phase difference between the reference clock CLK_REF and the feedback clock CLK_FED.
Since the circuit configurations of the first and second D flip-flops 112 and 114 are well known, their detailed description is omitted for conciseness.
FIG. 3 is a circuit diagram of the VCO 150 illustrated in FIG. 1.
Referring to FIG. 3, the VCO 150 includes a plurality of PMOS transistors 152, a plurality of NMOS transistors 154, and a plurality of inverters 156. Each of the inverters has unit delay time according to a voltage level of the control voltage V_CTR. When the voltage level of the control voltage V_CTR increases, a large amount of current is supplied to the inverters of the VCO 150. Therefore, the delay time of each of the inverters becomes short and the VCO 150 generates the internal clock CLK_INN of a high frequency. On the other hand, when the voltage level of the control voltage V_CTR decreases, a small amount of current is supplied to the inverters. Therefore, the delay time of each of the inverters becomes long and the VCO 150 generates the internal clock CLK_INN of a low frequency.
The control voltage (V_CTR) terminal of the VCO 150 will be described below.
In the VCO 150, the voltage level of the control voltage V_CTR is made to a logic low level before the locking operation. This prevents undesired current consumption caused by unnecessary operations of the VCO 150 before the PLL operates.
In other words, since the control voltage V_CTR is inputted to gates of the plurality of NMOS transistors 154, the control voltage V_CTR is made to a logic low level before the PLL operates. If the control voltage V_CTR is inputted to the plurality of PMOS transistors 152, the control voltage V_CTR is made to a logic high level before the PLL operates.
The PLL of FIG. 3 performs the locking operation to increase the control voltage V_CTR of a logic low level up to a voltage level at which the internal clock CLK_INN of a desired target frequency can be generated. The time necessary to generate the control voltage V_CTR for generating the internal clock CLK_INN of the desired target frequency is defined as a locking time.
To meet the requirements of high-speed operation of semiconductor devices, it is necessary to rapidly generate the internal clock CLK_INN of a desired frequency at a fast speed by reducing the locking time. Thus, there is a need for techniques that can reduce the locking time.